core dump: misaligned load problem



  • the following error trace occurred to me when I use lvgl library,it happened when the following code executed:
    new_lv_task->task = task;
    how to solve this problem, is there any solution or any way to guide me to solute it?

    core dump: misaligned load
    Cause 0x0000000000000004, EPC 0x00000000800111f6
    reg[00](zero ) = 0xdf1c0ece1eb0e162, reg[01](ra   ) = 0x00000000800001de
    reg[02](sp   ) = 0x00000000800692e0, reg[03](gp   ) = 0x000000008001eb30
    reg[04](tp   ) = 0x00000000800497c0, reg[05](t0   ) = 0x0000000080008abe
    reg[06](t1   ) = 0x00000000800111e2, reg[07](t2   ) = 0x000619cb751a0000
    reg[08](s0/fp) = 0x00000000800057f2, reg[09](s1   ) = 0x0000000000000003
    reg[10](a0   ) = 0x0000000000000006, reg[11](a1   ) = 0x00000000800057f2
    reg[12](a2   ) = 0x0000000080069500, reg[13](a3   ) = 0x0000000080069600
    reg[14](a4   ) = 0x0000000000000003, reg[15](a5   ) = 0x0000000000000003
    reg[16](a6   ) = 0x00000000000000ff, reg[17](a7   ) = 0x0000000000000040
    reg[18](s2   ) = 0x00000000800018e0, reg[19](s3   ) = 0x000000000000001e
    reg[20](s4   ) = 0x0000000000000000, reg[21](s5   ) = 0x0000000000000000
    reg[22](s6   ) = 0x0000000000000000, reg[23](s7   ) = 0x0000000000000000
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000008001d140, reg[29](t4   ) = 0x000000000000ffff
    reg[30](t5   ) = 0x00000000000a0019, reg[31](t6   ) = 0x0010000100008410
    freg[00](ft0 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bae0()
    freg[02](ft2 ) = 0x0000000000000000(), freg[00]() = 0x000000008001baf0()
    freg[04](ft4 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bb00()
    [22:01:07.482] freg[06](ft6 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bb10()
    freg[08](fs0 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bb38()
    freg[10](fa0 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bb68()
    freg[12](fa2 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bb90()
    freg[14](fa4 ) = 0x41d73eed80000000(), freg[-1073741824]() = 0x000000008001bba0()
    freg[16](fa6 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bbb0()
    freg[18](fs2 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bbd8()
    freg[20](fs4 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bbe8()
    freg[22](fs6 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bbf8()
    freg[24](fs8 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bc08()
    freg[26](fs10) = 0x0000000000000000(), freg[00]() = 0x000000008001bc18()
    freg[28](ft8 ) = 0x0000000000000000(), freg[00]() = 0x000000008001bc40()
    freg[30](ft10) = 0x0000000000000000(), freg[00]() = 0x000000008001bc50()
    W (95499125) SYSCALL: sys_exit called by core 0 with 0x539
    
    

  • Staff

    you can use these code to deal with these error.

    but u'd better to align your data structure folowing risc-v standard

    handle_misaligned_load(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
    {
    	//notice this function only support 16bit or 32bit instruction
    
    	bool compressed = (*(unsigned short *)epc & 3) != 3;
    	bool fpu = 0; // load to fpu ?
    	uintptr_t addr = 0; // src addr
    	uint8_t src = 0; // src register
    	uint8_t dst = 0; // dst register
    	uint8_t len = 0; // data length
    	int offset = 0; // addr offset to addr in reg
    	bool unsigned_ = 0; //unsigned
    	uintptr_t data_load = 0;// real data load
    
    	if (compressed) {
    		// compressed instruction should not get this fault.
    		goto on_error;
    	} else {
    		uint32_t instruct = *(uint32_t *)epc;
    		uint8_t opcode = instruct&0x7F;
    
    		dst = (instruct >> 7)&0x1F;
    		len = (instruct >> 12)&3;
    		unsigned_ = (instruct >> 14)&1;
    		src = (instruct >> 15)&0x1F;
    		offset = (instruct >> 20);
    		switch (opcode) {
    		case 3://load
    			break;
    		case 7://fpu load
    			fpu = 1;
    			break;
    		default:
    			goto on_error;
    		}
    	}
    
    	if (offset >> 11)
    		offset = -(offset & 0x3FF);
    
    	addr = (uint64_t)((uint64_t)regs[src] + offset);
    
    	for (int i = 0; i <= len; ++i)
    		data_load |= *((uint8_t *)addr + i) << 8 * i;
    
    	if (!unsigned_) {
    		// adjust sign
    		if (((data_load >> ((len + 1) * 8 - 1)) & 1) == 1) {
    			// data is signed
    			data_load = (data_load & (1 << (((len + 1) * 8) - 2))) + 1; // to positive number
    			data_load = -data_load; // adjust back to negative
    		}
    	}
    
    	if (fpu)
    		fregs[dst] = data_load;
    	else
    		regs[dst] = data_load;
    
    	LOGV(TAG, "misaligned load recovered at %16lx", (uint64_t)epc);
    
    	return epc + (compressed ? 2 : 4);
    on_error:
    	dump_core("misaligned load", cause, epc, regs, fregs);
    	sys_exit(1337);
    	return epc;
    }
    
    
    handle_misaligned_store(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
    {
    	//notice this function only support 16bit or 32bit instruction
    
    	bool compressed = (*(unsigned short *)epc & 3) != 3;
    	bool fpu = 0; // store to fpu ?
    	uintptr_t addr = 0; // src addr
    	uint8_t src = 0; // src register
    	uint8_t dst = 0; // dst register
    	uint8_t len = 0; // data length
    	int offset = 0; // addr offset to addr in reg
    	uintptr_t data_store = 0;// real data store
    
    	if (compressed) {
    		// compressed instruction should not get this fault.
    		goto on_error;
    	} else {
    		uint32_t instruct = *(uint32_t *)epc;
    		uint8_t opcode = instruct&0x7F;
    
    		len = (instruct >> 12)&7;
    		dst = (instruct >> 15)&0x1F;
    		src = (instruct >> 20)&0x1F;
    		offset = ((instruct >> 7)&0x1F) | ((instruct >> 20)&0xFE0);
    		switch (opcode) {
    		case 0x23://store
    			break;
    		case 0x27://fpu store
    			fpu = 1;
    			break;
    		default:
    			goto on_error;
    		}
    	}
    
    	if (offset >> 11)
    		offset = -(offset & 0x3FF);
    
    	addr = (uint64_t)((uint64_t)regs[dst] + offset);
    
    
    	if (fpu)
    		data_store = fregs[src];
    	else
    		data_store = regs[src];
    
    	for (int i = 0; i <= len; ++i)
    		*((uint8_t *)addr + i) = (data_store >> (i*8)) & 0xFF;
    
    	LOGV(TAG, "misaligned store recovered at %16lx", (uint64_t)epc);
    
    	return epc + (compressed ? 2 : 4);
    on_error:
    	dump_core("misaligned store", cause, epc, regs, fregs);
    	sys_exit(1337);
    	return epc;
    }
    
    
    

  • Staff

    Re: core dump: misaligned load problem

    It looks like error memory access (from information core dump: misaligned load)
    You could find EPC=0x00000000800111f6
    Assume your out put elf file is output
    Use riscv64-unknown-elf-objdump -lSD output > output.S to get decompile file, and find string 800111f6. Then you can find where the error is (including line number)



  • OK, I have solved this problem myself, It just I'm not familiar with this lib, and the documents has not mentioned particularly for 64 bit CPU😅 . Just add definition like:

    #define LV_MEM_ENV64 1
    

    witch is only usable for this lib.