Partially dedicated pin to ball mapping of the SPI0 functionality. Idea?



  • What is the idea of the partially dedicated pin to ball mapping of the SPI0 pins (SPI0_D0 to SPI0_D7. The SPI0_CLK and the SPI0_nCSx signals have no dedicated mapping)?- Based on the documentation and the source code it is possible to map even the SPI0_D0-D7 signals to each IO ball. In contrast on the the demo board these signals are used as parallel interface to the LCD. Are there special connections to these balls for the video output?- I would just like to understand it from a technical standpoint.



  • @vowstar Thank you for the table. I just try to find the optimal pinout for my design.


  • Staff |  Mod

    @q2222 said in Partially dedicated pin to ball mapping of the SPI0 functionality. Idea?:

    @vowstar: Thank you for your answer. Is there a best location for the fast SPI0_CLK signal, too?

    Certainly. SPI0_CLK could directly out put at IO_27. SPI_0 CS must use FPIOA to mapping, no black magic.

    Note: Bypass function must enabled in sysctl to take effect. If it bypass, the signal will ignore FPIOA and directly output/input.

    In most cases, such a setup is not necessary. FPIOA can map it everywhere.

    This table described optimal recommendation IO functions.

    |   IO    | OPTIMAL FUNCTION NAME |                   DESCRIPTION                    |     |
    | ------- | --------------------- | ------------------------------------------------ | --- |
    | 0       | JTAG_TCLK             | JTAG input clock bypass                          |     |
    | 1       | JTAG_TDI              |                                                  |     |
    | 2       | JTAG_TMS              |                                                  |     |
    | 3       | JTAG_TDO              |                                                  |     |
    | 4       | UARTHS_RX             |                                                  |     |
    | 5       | UARTHS_TX             |                                                  |     |
    | 6       | I2C0_SCLK/SCCB_SCLK   |                                                  |     |
    | 7       | I2C0_SDA/SCCB_SDA     |                                                  |     |
    | 20      | CMOS_XCLK             | DVP output clock bypass                          |     |
    | 21      | CMOS_PCLK             | DVP input clock bypass                           |     |
    | 27      | SPI0_SCLK             | SPI0 output clock bypass                         |     |
    | 31      | SPI2_SCLK             | SPI2 input clock bypass                          |     |
    | 32      | SPI1_SCLK             | SPI1 output clock bypass                         |     |
    | 33      | I2S0_SCLK             | I2S0 output sclk bypass                          |     |
    | 34      | I2S0_MCLK             | I2S0 output mclk bypass                          |     |
    | 35      | I2S1_SCLK             | I2S1 output sclk bypass                          |     |
    | 36      | I2S1_MCLK             | I2S1 output mclk bypass                          |     |
    | 37      | I2S2_SCLK             | I2S2 output sclk bypass                          |     |
    | 38      | I2S2_MCLK             | I2S2 output mclk bypass                          |     |
    | DVP_D0  | CMOS_D0               | Input only                                       |     |
    | DVP_D1  | CMOS_D1               | Input only                                       |     |
    | DVP_D2  | CMOS_D2               | Input only                                       |     |
    | DVP_D3  | CMOS_D3               | Input only                                       |     |
    | DVP_D4  | CMOS_D4               | Input only                                       |     |
    | DVP_D5  | CMOS_D5               | Input only                                       |     |
    | DVP_D6  | CMOS_D6               | Input only                                       |     |
    | DVP_D7  | CMOS_D7               | Input only                                       |     |
    | SPI0_D0 | LCD_D0                | Output only                                      |     |
    | SPI0_D1 | LCD_D1                | Output only                                      |     |
    | SPI0_D2 | LCD_D2                | Output only                                      |     |
    | SPI0_D3 | LCD_D3                | Output only                                      |     |
    | SPI0_D4 | LCD_D4                | Output only                                      |     |
    | SPI0_D5 | LCD_D5                | Output only                                      |     |
    | SPI0_D6 | LCD_D6                | Output only                                      |     |
    | SPI0_D7 | LCD_D7                | Output only                                      |     |
    


  • @vowstar: Thank you for your answer. Is there a best location for the fast SPI0_CLK signal, too?


  • Staff |  Mod

    SPI D[7:0] also can mapped to everywhere in IO[47:0]. It designed for best signal quality