freeRTOS i2c read problem



  • Hello,
    I try to run this example on my Maixduino, but I can't. Could you please share to my an example of I2C read-write mini example?
    original code:

    handle_t i2c = io_open("/dev/i2c0");
    /* The i2c peripheral address is 0x32, 7-bit address, rate 200K */
    handle_t dev0 = i2c_get_device(i2c, "/dev/i2c0/dev0", 0x32, 7);
    i2c_dev_set_clock_rate(dev0, 200000);
    
    uint8_t reg = 0;
    uint8_t data_buf[2] = { 0x00,0x01 };
    data_buf[0] = reg;
    /* Write 0x01 to the 0 register */
    io_write(dev0, data_buf, 2);
    /* Read 1 byte data from 0 register */
    i2c_dev_transfer_sequential(dev0, &reg, 1, data_buf, 1);
    

    and My code:

    void vBme280TaskCore0(void *params) {
      handle_t i2c1 = io_open("/dev/i2c1");
      /* The i2c peripheral address is 0x32, 7-bit address, rate 200K */
      handle_t dev0 = i2c_get_device(i2c1, 0x76, 7);
      i2c_dev_set_clock_rate(dev0, 200000);
      for (;;) {
        /* TODO */
        uint8_t data_buf[2] = {0x00, 0x00};
        data_buf[0] = 0xD0;
        /* Write 0x01 to the 0 register */
        //io_write(dev0, data_buf, 1);
        /* Read 1 byte data from 0 register */
        i2c_dev_transfer_sequential(dev0, data_buf, 1, data_buf, 1);
    
        printf("%d-%d\r\n", data_buf[0], data_buf[1]);
    
        vTaskDelay(pdMS_TO_TICKS(3000));
      }
    }
    

    and dump:

    core 0, core dump: misaligned load
    Cause 0x0000000000000004
    reg[00](mpec ) = 0x000000008001e74a, reg[01](ra   ) = 0x000000008001e7d8
    reg[02](sp   ) = 0x00000000800ac680, reg[03](gp   ) = 0xa5a5a5a5a5a5a5a5
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080012b16
    reg[06](t1   ) = 0x000000000000000f, reg[07](t2   ) = 0x0000000080020a42
    reg[08](s0/fp) = 0x00000000a708c383, reg[09](s1   ) = 0x000000008004f288
    reg[10](a0   ) = 0x0000000000000008, reg[11](a1   ) = 0x0000000000000000
    reg[12](a2   ) = 0x000000008004c388, reg[13](a3   ) = 0x0000000000000010
    reg[14](a4   ) = 0x0000000000000008, reg[15](a5   ) = 0x000000008004c37a
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x00000000800ada48
    reg[18](s2   ) = 0x000000008004c37a, reg[19](s3   ) = 0x00000000000002b7
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x00000000000000ff, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000008001f88c, reg[29](t4   ) = 0x0000000000000000
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0xa5a5a5a500000000, freg[01](ft1 ) = 0xa5a5a5a500000000
    freg[02](ft2 ) = 0xa5a5a5a500000000, freg[03](ft3 ) = 0xa5a5a5a500000000
    freg[04](ft4 ) = 0xa5a5a5a500000000, freg[05](ft5 ) = 0xa5a5a5a500000000
    freg[06](ft6 ) = 0xa5a5a5a500000000, freg[07](ft7 ) = 0xa5a5a5a500000000
    freg[08](fs0 ) = 0xa5a5a5a500000000, freg[09](fs1 ) = 0xa5a5a5a500000000
    freg[10](fa0 ) = 0xa5a5a5a500000000, freg[11](fa1 ) = 0xa5a5a5a500000000
    freg[12](fa2 ) = 0xa5a5a5a500000000, freg[13](fa3 ) = 0xa5a5a5a500000000
    freg[14](fa4 ) = 0xa5a5a5a500000000, freg[15](fa5 ) = 0xa5a5a5a500000000
    freg[16](fa6 ) = 0xa5a5a5a500000000, freg[17](fa7 ) = 0xa5a5a5a500000000
    freg[18](fs2 ) = 0xa5a5a5a500000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0xa5a5a5a500000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0xffffffff00000000
    freg[28](ft8 ) = 0xa5a5a5a500000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x0000000080053d58, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800adbb8
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x000000008004f1f8
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0x0000000000000000
    reg[12](a2   ) = 0x0000000000000000, reg[13](a3   ) = 0x0000000000000000
    reg[14](a4   ) = 0x00000000800adbb8, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x0000000080054240, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000000, reg[29](t4   ) = 0x0000000000000001
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0xffffffff00000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x00000000800537f8, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x00000000800ae258
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0xffffffffffffffff
    reg[12](a2   ) = 0x0000000000000004, reg[13](a3   ) = 0x0000000080053ce0
    reg[14](a4   ) = 0x0000000000000000, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x0000000080053ce0, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000001, reg[29](t4   ) = 0x0000000000000002
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x0000000080050cf8, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x00000000800ae258
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0xffffffffffffffff
    reg[12](a2   ) = 0x0000000000000004, reg[13](a3   ) = 0x00000000800511e0
    reg[14](a4   ) = 0x0000000000000000, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x00000000800511e0, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000009, reg[29](t4   ) = 0x000000000000000a
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x0000000080050798, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x00000000800ae258
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0xffffffffffffffff
    reg[12](a2   ) = 0x0000000000000004, reg[13](a3   ) = 0x0000000080050c80
    reg[14](a4   ) = 0x0000000000000000, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x0000000080050c80, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000000000000a, reg[29](t4   ) = 0x000000000000000b
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x0000000080050238, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x00000000800ae258
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0xffffffffffffffff
    reg[12](a2   ) = 0x0000000000000004, reg[13](a3   ) = 0x0000000080050720
    reg[14](a4   ) = 0x0000000000000000, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x0000000080050720, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000000000000b, reg[29](t4   ) = 0x000000000000000c
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x000000008004fcd8, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x00000000800ae258
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0xffffffffffffffff
    reg[12](a2   ) = 0x0000000000000004, reg[13](a3   ) = 0x00000000800501c0
    reg[14](a4   ) = 0x0000000000000000, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x00000000800501c0, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000000000000c, reg[29](t4   ) = 0x000000000000000d
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](ra   ) = 0x0000000080034f22
    reg[02](sp   ) = 0x000000008004f778, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000080035238, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x00000000800ae3e0, reg[09](s1   ) = 0x00000000800ae258
    reg[10](a0   ) = 0x0000000000000001, reg[11](a1   ) = 0xffffffffffffffff
    reg[12](a2   ) = 0x0000000000000004, reg[13](a3   ) = 0x000000008004fc60
    reg[14](a4   ) = 0x0000000000000000, reg[15](a5   ) = 0x0000000000000004
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000004, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x000000008004fc60, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000000000000d, reg[29](t4   ) = 0x000000000000000e
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: breakpoint
    Cause 0x0000000000000003
    reg[00](mpec ) = 0x000000008000a7cc, reg[01](core 0, core dump: fault load
    Cause 0x0000000000000005
    reg[00](mpec ) = 0x0000000080001ffe, reg[01](ra   ) = 0x0000000080001c2e
    reg[02](sp   ) = 0x000000008004eec8, reg[03](gp   ) = 0x000000008004eec8
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000000000000, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x0000000080001bee, reg[09](s1   ) = 0x000000008004f180
    reg[10](a0   ) = 0x0000000000000073, reg[11](a1   ) = 0x0000000000000025
    reg[12](a2   ) = 0x0000000000006009, reg[13](a3   ) = 0xfffffffffffffffe
    reg[14](a4   ) = 0x0000000000006008, reg[15](a5   ) = 0xffffffffffffffff
    reg[16](a6   ) = 0x0000000000000001, reg[17](a7   ) = 0x00000000800376e0
    reg[18](s2   ) = 0x0000000000000000, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x000000008004f700, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x000000000000000f, reg[29](t4   ) = 0x0000000000000010
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0x0000000000000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000000000000000
    freg[18](fs2 ) = 0x0000000000000000, freg[19](fs3 ) = 0x0000000000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000000000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0xffffffff00000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: misaligned load
    Cause 0x0000000000000004
    reg[00](mpec ) = 0x0000000080012bb2, reg[01](ra   ) = 0x0000000080000dda
    reg[02](sp   ) = 0x000000008004ec18, reg[03](gp   ) = 0x000000008004ec18
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000000000000, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x000000008004eec8, reg[09](s1   ) = 0x000000008004f180
    reg[10](a0   ) = 0x0000000080036dc0, reg[11](a1   ) = 0x000000004fd55921
    reg[12](a2   ) = 0x0000000080036dc0, reg[13](a3   ) = 0x000000008004ee50
    reg[14](a4   ) = 0x000000008004df58, reg[15](a5   ) = 0x6363376130303031
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000000, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x000000008004f700, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000010, reg[29](t4   ) = 0x0000000000000011
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0xffffffff00000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000001000000000
    freg[18](fs2 ) = 0x6666666600000000, freg[19](fs3 ) = 0x3030303000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000001000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: misaligned load
    Cause 0x0000000000000004
    reg[00](mpec ) = 0x0000000080012bb2, reg[01](ra   ) = 0x0000000080000dda
    reg[02](sp   ) = 0x000000008004e968, reg[03](gp   ) = 0x000000008004e968
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000000000000, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x000000008004ec18, reg[09](s1   ) = 0x000000008004f180
    reg[10](a0   ) = 0x0000000080036dc0, reg[11](a1   ) = 0x0000000054aaf151
    reg[12](a2   ) = 0x0000000080036dc0, reg[13](a3   ) = 0x000000008004eba0
    reg[14](a4   ) = 0x000000008004df58, reg[15](a5   ) = 0x6363376130303031
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000000, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x000000008004f700, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000011, reg[29](t4   ) = 0x0000000000000012
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0xffffffff00000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000001000000000
    freg[18](fs2 ) = 0x3030303000000000, freg[19](fs3 ) = 0x3030303000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000001000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: misaligned load
    Cause 0x0000000000000004
    reg[00](mpec ) = 0x0000000080012bb2, reg[01](ra   ) = 0x0000000080000dda
    reg[02](sp   ) = 0x000000008004e6b8, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000000000000, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x000000008004e968, reg[09](s1   ) = 0x000000008004f180
    reg[10](a0   ) = 0x0000000080036dc0, reg[11](a1   ) = 0x0000000059808985
    reg[12](a2   ) = 0x0000000080036dc0, reg[13](a3   ) = 0x000000008004e8f0
    reg[14](a4   ) = 0x000000008004df58, reg[15](a5   ) = 0x6363376130303031
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000000, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x000000008004f700, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000012, reg[29](t4   ) = 0x0000000000000013
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0xffffffff00000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000001000000000
    freg[18](fs2 ) = 0x3030303000000000, freg[19](fs3 ) = 0x3030303000000000
    freg[20](fs4 ) = 0x0000ffff00000000, freg[21](fs5 ) = 0x0000001000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    core 0, core dump: misaligned load
    Cause 0x0000000000000004
    reg[00](mpec ) = 0x0000000080012bb2, reg[01](ra   ) = 0x0000000080000dda
    reg[02](sp   ) = 0x000000008004e408, reg[03](gp   ) = 0x0000000000000000
    reg[04](tp   ) = 0x0000000000000000, reg[05](t0   ) = 0x0000000080000c82
    reg[06](t1   ) = 0x0000000000000000, reg[07](t2   ) = 0x00000000800004d0
    reg[08](s0/fp) = 0x000000008004e6b8, reg[09](s1   ) = 0x000000008004f180
    reg[10](a0   ) = 0x0000000080036dc0, reg[11](a1   ) = 0x000000005e5621c3
    reg[12](a2   ) = 0x0000000080036dc0, reg[13](a3   ) = 0x000000008004e640
    reg[14](a4   ) = 0x000000008004df58, reg[15](a5   ) = 0x6363376130303031
    reg[16](a6   ) = 0x0000000000000000, reg[17](a7   ) = 0x0000000080037ac0
    reg[18](s2   ) = 0x0000000000000000, reg[19](s3   ) = 0xffffffffffffffff
    reg[20](s4   ) = 0x0000000000000007, reg[21](s5   ) = 0x0000000000000001
    reg[22](s6   ) = 0x000000008004f700, reg[23](s7   ) = 0x00000000000007f8
    reg[24](s8   ) = 0x0000000000000000, reg[25](s9   ) = 0x0000000000000000
    reg[26](s10  ) = 0x0000000000000000, reg[27](s11  ) = 0x0000000000000000
    reg[28](t3   ) = 0x0000000000000013, reg[29](t4   ) = 0x0000000000000014
    reg[30](t5   ) = 0x0000000000000010, reg[31](t6   ) = 0x0000000000000000
    freg[00](ft0 ) = 0x0000000000000000, freg[01](ft1 ) = 0x0000000000000000
    freg[02](ft2 ) = 0x0000000000000000, freg[03](ft3 ) = 0x0000000000000000
    freg[04](ft4 ) = 0x0000000000000000, freg[05](ft5 ) = 0x0000000000000000
    freg[06](ft6 ) = 0x0000000000000000, freg[07](ft7 ) = 0x0000000000000000
    freg[08](fs0 ) = 0x0000000000000000, freg[09](fs1 ) = 0xffffffff00000000
    freg[10](fa0 ) = 0x0000000000000000, freg[11](fa1 ) = 0x0000000000000000
    freg[12](fa2 ) = 0x0000000000000000, freg[13](fa3 ) = 0x0000000000000000
    freg[14](fa4 ) = 0x0000000000000000, freg[15](fa5 ) = 0x0000000000000000
    freg[16](fa6 ) = 0x0000000000000000, freg[17](fa7 ) = 0x0000001000000000
    freg[18](fs2 ) = 0x3030303000000000, freg[19](fs3 ) = 0x3030303000000000
    freg[20](fs4 ) = 0x0000000000000000, freg[21](fs5 ) = 0x0000001000000000
    freg[22](fs6 ) = 0x0000000000000000, freg[23](fs7 ) = 0x0000000000000000
    freg[24](fs8 ) = 0x0000000000000000, freg[25](fs9 ) = 0x0000000000000000
    freg[26](fs10) = 0x0000000000000000, freg[27](fs11) = 0x0000000000000000
    freg[28](ft8 ) = 0x0000000000000000, freg[29](ft9 ) = 0x0000000000000000
    freg[30](ft10) = 0x0000000000000000, freg[31](ft11) = 0x0000000000000000
    

    Thanks



  • I figured it out myself:

    #include <FreeRTOS.h>
    #include <devices.h>
    #include <fpioa.h>
    #include <pin_cfg.h>
    #include <stdio.h>
    #include <task.h>
    
    #define SDA (31)
    #define SCL (30)
    #define DEVICE_ADDRESS 0x68
    
    void vI2cTaskCore1(void *arg) {
      const TickType_t xFrequency = 1000;
      TickType_t xLastWakeTime;
      /* Initialise the xLastWakeTime variable with the current time. */
      xLastWakeTime = xTaskGetTickCount();
    
      handle_t i2c0 = io_open("/dev/i2c0");
      uint8_t sda = SDA;
      uint8_t scl = SCL;
      fpioa_set_function(sda, FUNC_I2C0_SDA);
      fpioa_set_function(scl, FUNC_I2C0_SCLK);
    
      uint8_t writeBuffer[2];
      uint8_t readBuffer[2];
    
      handle_t device= i2c_get_device(i2c0, DEVICE_ADDRESS, 7);
    
      while (1) {
        writeBuffer[0] = 0x01; /* Register */
        io_write(device, writeBuffer, 1);
        io_read(device, readBuffer, 2);
        printf("Values %d, %d\r\n", readBuffer[0], readBuffer[1]);
    
        /* Wait for the next cycle. */
        vTaskDelayUntil(&xLastWakeTime, pdMS_TO_TICKS(xFrequency));
      }
    }
    
    int main() {
      BaseType_t xReturn;
    
      xReturn = xTaskCreateAtProcessor(CORE_1, &vI2cTaskCore1, "vI2cTaskCore1", 512, NULL, 2, NULL);
      if (xReturn != pdPASS) {
        printf("Task %s run problem\r\n", "vI2cTaskCore1");
      }
    
      for (;;) {
      }
    }